1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device in which a V-NPN and a V-PNP bipolar transistor are formed on one and the same substrate.
2. Background of the Invention
In the past, semiconductor devices in which a V-NPN and a V-PNP bipolar transistor are formed on one and the same substrate have been widely known. In these devices, the method of forming the emitter of a bipolar transistor is, for example, that of causing solid-phase diffusion of an impurity from a polysilicon layer into the single-crystal silicon layer (polysilicon emitter type, to be described herein).
Using the above-noted method, to form a V-NPN and a V-PNP transistor on a single substrate, n-type and p-type impurities are introduced into a prescribed region of a polysilicon layer, thereby requiring two masking processes.
To use the so-called SIC (selectively implanted collector) method, in which improves the transistor characteristics by increasing the concentration of collector impurity directly below the emitter region, in order to introduce an impurity into the V-NPN region the V-PNP region, it is necessary to have two additional masking processes, and the formation of high-performance V-NPN and V-PNP transistors on one and the same substrate is accompanied by the problem of a high number of masking steps.
An example of the past method of manufacturing a semiconductor device having a V-NPN and a V-PNP transistor formed on a single substrate and in which the above-noted SIC is formed directly below the emitter region is described below.
FIG. 17 through FIG. 25 are cross-section views of the manufacturing process steps that illustrate the past method of manufacturing.
First, as shown in FIG. 17, a field oxide film 2 that defines element separation is formed on a p-type silicon substrate 1, after which the substrate 1 is oxidized to form an oxide film 3 having a thickness of 50 to 200 Angstroms.
Then, an n-type collection region 4, a high-concentration p-type base extension region 5, a p-type base region 6, and a high-concentration n-type collection extension region 7 of a V-NPN bipolar transistor, and an n-type element separation region 8, a p-type collection region 9, a high-concentration n-type base extension region 10, an n-type base region 11, and a high-concentration p-type collector extension region 12 of a V-PNP bipolar transistor are formed, respectively.
Next, as shown in FIG. 18, etching operation is performed using the resist film 38 formed on the oxide film 13 having a thickness of 500 to 1000 Angstroms and formed over the entire surface of the substrate, as a mask, thereby removing the oxide films 3 and 13, so as to form an emitter contact 15 of the V-NPN transistor and an emitter contact 39 of the V-PNP transistor.
Next, as shown in FIG. 19, resist 40 is used as a mask to ion implant phosphorus, using an energy of 200 to 400 keV, with a dose of 1 to 5.times.10.sup.12 cm.sup.-2 thereby forming an n-type SIC region 16.
Next, as shown in FIG. 20, resist 41 is used as a mask to ion implant boron, using an energy of 60 to 150 keV, with a dose of 1 to 5.times.10.sup.12 cm.sup.-2, thereby forming a p-type SIC region 37.
Next, as shown in FIG. 21, a polysilicon layer 17 having a thickness of 2000 to 3000 Angstroms is formed over the entire substrate surface, including the emitter contacts 15 and 39.
Next, as shown in FIG. 22, resist 42 is used as a mask to ion implant boron with a dose of 1 to 2.times.10.sup.16 cm.sup.-2.
Next, as shown in FIG. 23, resist 43 is used as a mask to ion implant arsenic with a dose of 1 to 2.times.10.sup.16 cm.sup.-2.
Next, as shown in FIG. 24, resist 43 is used as a mask to etch the polysilicon layer 17 so as to form an emitter electrode 20 of an V-NPN transistor and an emitter electrode 44 of a V-PNP transistor.
After the above, heat treating at 900 to 1000.degree. C. is performed in an atmosphere of nitrogen to cause diffusion of impurities in the polysilicon layers 17 and 25, thereby forming an n-type emitter region 27 and a p-type emitter region 28.
Next, in an interlayer insulation film 29 formed over the elements formed by the above-noted process steps, a contact 30 is formed, after which a plug 31 is formed of tungsten or the like, and metal interconnects 32 are formed, thereby achieving the semiconductor device shown in FIG. 25.
In the above-noted method of manufacturing, in order to improve the transistor characteristics, an SIC region is formed in both the V-NPN transistor and the V-PNP transistor. The conductivity types of the impurity that is ion implanted into these regions are different, and two masking operations are required to form the SIC (FIG. 19 and FIG. 20).
Additionally, the formation of the emitter electrode 20 also requires different masking operations in which ion implantation must be done, respectively (FIG. 22 and FIG. 23).
In the prior art method such as described above, there exists the problem of requiring a large number of masking process steps in order to form a V-NPN transistor and a V-PNP transistor on a single substrate.
In Japanese Unexamined Patent Publications (KOKAI) No. 62-86753 and No. 4-18752, there is language describing a semiconductor device in which an NPN transistor and a PNP transistor are formed on a single semiconductor substrate. However, there is no language with regard to a semiconductor device having an SIC, and no language with regard to reducing the number of process steps when manufacturing a semiconductor device having an SIC.
Accordingly, and in consideration of the above-noted drawbacks of the prior art, it is an object of the present invention to provide a method for manufacturing a semiconductor device having an NPN transistor and a PNP transistor, both of which have an SIC region, on one and the same substrate, featuring a shortened manufacturing process with greatly reduced manufacturing cost, without sacrificing performance.